• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    TEST METHOD OF AN ELEVATOR INSTALLATION AND MONITORING ASSEMBLY FOR PERFORMING THE TEST METHOD. The present invention relates, in a first aspect, to a method of testing an elevator installation with a control unit (11) and at least one bus node (13). This bus node (13) has a first microprocessor (14) and a second microprocessor (15). The control unit (11) and the bus node (13) communicate via a bus (12). Furthermore, the first microprocessor (14) and the second microprocessor (15) are connected without interruption via a signal line (18). The test method comprises the following steps: by the control unit (11) a standard signal is transmitted to the first microprocessor (14), the first microprocessor (14) transmits the signal to the second microprocessor (15) and the second microprocessor ( 15) makes the signal available to the control unit (11). Finally, the control unit (11) checks whether the signal provided corresponds to a signal expected by the control unit (11). A second aspect refers to a monitoring set for carrying out the test method.
    公开号:BR112014002825B1
    申请号:R112014002825-7
    申请日:2012-07-24
    公开日:2021-04-20
    发明作者:Astrid Sonnenmoser；David Michel；Martin Hess
    申请人:Inventio Ag；
    IPC主号:
    专利说明:

    [0001] The present invention relates to a test method of an elevator installation and a monitoring set for carrying out the test method.
    [0002] Conventional elevator installations feature safety circuits that are made up of safety elements connected in series. These safety elements control, for example, the state of pit or cabin doors. The security element of this type can be a contact. An open contact shows that, for example, a port is open and that a potentially inadmissible port state has arisen. If an inadmissible open state of the doors is now detected with the open contact, the safety circuit will be interrupted. This will have the consequence that the activation or braking, acting on the displacement of an elevator cabin, produces the stoppage of this cabin.
    [0003] From the patent WO 2009/010410 A1 it became known a monitoring set for an elevator installation that has a control unit as well as at least one bus node and a busbar. The bus enables communication between the bus node and the control unit. Via the safety element, the bus node controls, for example, the well gate status. The bus node has a first microprocessor and a second microprocessor. In this case, the first microprocessor is shaped in such a way that it interprets standardized digital signals from the control unit, transforming it into an analogue signal and thus subjecting the safety element. The second microprocessor in turn measures the analogue signal after the safety element and transforms it into a digital signal. The second microprocessor makes this digital information available to the control unit. This information will either be sent by the bus nodes as digital signals to the control unit or will be requested by the control unit through consultation. When the safety switch is open and the second microprocessor therefore does not measure an analog signal, it spontaneously sends negative status information to the control unit.
    [0004] In order to ensure a safe operation of the elevator installation, the perfect functional capacity of the two microprocessors, especially the second microprocessor, in the appearance of a negative status state, that is, when the safety improvement is open, it will have to be repeated times tested. In WO 2009/010410 A1 a test of a standard signal is proposed in this case. In this test, the control unit transmits different standardized digital signals to the first microprocessor. The control unit, based on the digital signals offered or sent by the second microprocessor, will be able to verify that the two microprocessors correctly transform the standardized variable signals. A signal standardized with the value O, that is, a faulty value represents a special case, in which the spontaneous response of the second microprocessor is provoked. The control unit will send to the first microprocessor a standardized digital signal with the fault value which it will transform into an analogue standardized signal with fault value and with this it acts on the safety element. In this way, an open security element will be simulated. The control unit expects the second microprocessor, by virtue of the standardized analogue signal registered with the fault value, to respond spontaneously by sending a digital signal to this control unit. If this hold position of the control unit is fulfilled and if the other standardized signals are correctly transformed, the control unit can assume that both the first and the second microprocessor are operating perfectly.
    [0005] A disadvantage of these testable bus nodes remains their expensive production. In mass production of these bus nodes, small cost savings have an important price effect.
    [0006] It is, therefore, the task of the present invention to offer a test process for an elevator installation, that is, a monitoring set to carry out the test method that enables a favorable production of the monitoring set, especially of the bus nodes .
    [0007] A first aspect refers to a monitoring set of an elevator installation with a control unit and at least one bus node. The bus node has the first microprocessor and a second microprocessor. The control unit and the bus node communicate over a bus. The monitoring set is distinguished by the fact that the first microprocessor and the second microprocessor are interconnected without interruption via a signaling line.
    [0008] With the expression signaling line without interruption, it must be understood here a signaling line that presents a continuous conductor which, as here, for example, directly connects two microprocessors. Especially here considered a signaling line that is made up of several constituted partial elements that are in contact not considered as conductors, that is, an uninterrupted and continuous signaling line. An uninterrupted signal line therefore does not include partial elements such as switches, safety elements or similar units, even when these are in contact with the signal line or parts of this line.
    [0009] In a second aspect, the monitoring set is part of a test method. The method comprises the following steps: by the control unit a standard signal is transmitted to the first microprocessor, the first microprocessor transfers the signal through the signal line to the second microprocessor and the second microprocessor makes the signal available to the control unit. Finally, the control unit checks whether the offered signal matches a signal expected by the control unit.
    [00010] The advantage of this monitoring set is that in the test method the standardized signal sent by the control unit and then transformed into the first microprocessor, will be sent by the first microprocessor, through a signaling line, to the second microprocessor. It so happens that this signaling line uninterruptedly interconnects the first microprocessor and the second microprocessor, so that the second signaling line directly interconnects the first microprocessor and the second microprocessor. The internal arrangement based on bus nodes of the signaling line is particularly advantageous. As this signaling line does not include additional elements such as a safety element or a key, and can be formed very short, its resistance is very low. Therefore, signals can also be sent with reduced power from the first to the second microprocessor. Correspondingly, compared to the bus node initially described, a reduced-capacity signal amplifier can be employed. The bus node can therefore be produced in an especially advantageous way.
    [00011] In a first presentation of the test method, the control unit sends a standardized signal as a first value to a bus node. In response, the bus node provides a signal as a second value. The control unit will then check whether the second value offered can be allocated to the first value sent. The second value should then be allocated to the first value when the second value offered matches a second value expected by the control unit in response to the first value. If the second offered amount can be allocated, the test will have passed. When the second amount offered cannot be allocated to the first amount, the test is deemed not to have passed.
    [00012] In addition, the first microprocessor of the bus node interprets the standard signal sent by the control unit with the first value and transforms this standard signal into an internal signal of the bus node that is transmitted by the first microprocessor to the second microprocessor through of the signal line. The second microprocessor will interpret this signal, transform it into a response signal with a second value and provide the response signal to the control unit.
    [00013] In a first preferred embodiment, the standard signal represents a digital current value. The first microprocessor will read this current value and transform it into an analog current signal with a current intensity that corresponds to the first digital current value of the standard signal. The first microprocessor will clamp the signal line with the analog current signal. The second microprocessor will measure the current strength of the analog current signal and transform the measured current strength into a digital signal with the second current value corresponding to the measured current value. This digital signal is provided by the second microprocessor to the control unit as a response signal. The control unit will check if the second current value can be allocated, ie it corresponds to the first sent current value.
    [00014] Instead of a current value, a standardized voltage value, a frequency value, an activation duration value or a code value can also be indicated. Correspondingly, the first microprocessor will subject the signal line with an analog signal covering one of these values.
    [00015] Alternatively the first microprocessor will subject the signal line with a digital signal having the code value that preferably corresponds to a code value of the standardized signal. This code value will be interpreted by the second microprocessor and correspondingly will be offered to the control unit. The transformation of the digital signal into an analog signal and back into a digital signal in the first, that is, in the second microprocessor, is dispensed with here. In this alternative, the code value can represent a number or a sequence of random numbers.
    [00016] Preferably, in this test method, at least two queries will be performed with two different default values. If the value of the response signal offered can be allocated twice to the two different values of the standard signals, the test will be considered as passed.
    [00017] Preferably, the control unit will perform the bus node test method at recurring time intervals. The time interval will be according to the reliability of the first and second microprocessor used and is between 1  and 100 s.
    [00018] In the event of a negative verification of the offered digital signal, i.e., the test does not pass, measures will be taken by the control unit to make the elevator installation be positioned in a safe operational state.
    [00019] In another conformation of the test method, the control unit sends a standard signal containing a fault value to a bus node. In this test, the signal provided by a safety element to the second microprocessor, representing an unsafe state of the elevator installation, will be simulated. In this case, the control unit expects the tested bus node to spontaneously transmit a response signal to the control unit. A current value of 0, a voltage value of 0, a frequency value of 0 or a switch-on duration value correspond to a fault value of this nature. By means of one of these 0 values, for example, an open security element will be simulated that is shaped like a security key. Likewise, a code value can present an unsafe elevator installation value, that is, a faulty value.
    [00020] In this case, the control unit sends a standard signal with a fault value to the first microprocessor. This will read the value and subject the internal signaling line of the bus node to a signal that has a faulty value. The second microprocessor will interpret this signal as the fault value and spontaneously transmit a response signal to the control unit. Here too, the signal transmitted by the first microprocessor via the second signal line is an analogue signal or a digital signal.
    [00021] Next, the invention will be explained based on several examples of execution and two figures and will also be described in detail. The figures show:
    [00022] Figure 1 - schematic view of a first modality of the monitoring set and,
    [00023] Figure 2 - schematic view of the second version of the monitoring set.
    [00024] As initially described, the present monitoring set 10 and the present test method are specially adapted to be employed in elevator installations.
    [00025] Figure 1 presents a first mode of monitoring set 10. Monitoring set 10 has a control unit 11 and at least one bus node 13. The communication between the control unit 11 and the bus node bus 13 takes place via a bus 12. Therefore, between the bus node 13 and the control unit 11 data can be sent over the bus in both directions. The bus node 13 itself comprises the first microprocessor 14 and a second microprocessor 15. The first microprocessor 14, i.e. the second microprocessor 15 is shaped in such a way that the first receives standard signals from the control unit 11 and the latter provides information signals as response signals to the control unit 11. In addition, the bus node 13 via an external signaling line 17.1, 17.2 of the bus node is joined with a safety element 16, a first part 17.1 of the external signal line of the bus node interconnects the first microprocessor 14 as security element 16 and a second part 17.2 of the external signal line of the bus node interconnects the security element 16 with the second microprocessor 15. Finally, the first microprocessor 14 and the second microprocessor 15 are interconnected without interruption via an internal signaling line 18 of the bus node.
    [00026] The control unit 11, the bus 12 and at least one bus node 13 constitute a bus system. Within this bus system, each bus node 13 has an unambiguous address of its own. Through this address, message formation between control 11 and bus node 13 is verified.
    [00027] The control unit 11 transmits 12 digital standard signals over the bus to the first microprocessor 14. In this case, the control unit addresses a determined bus node 13 and communicates the standard signal to the first microprocessor 14. The first microprocessor 14 will receive this standard signal and generate an analogous signal corresponding to the standard signal that will be applied to the external signaling line 17.1, 17.2 of the bus node. The analog signal can be a certain voltage, current strength, frequency or switch-on duration value.
    [00028] Security element 16 displays the status of a security-relevant element. Thus, the safety element 16 is used, for example, as a door contact, bolt contact, damper contact, flapper contact, displacement key or emergency stop key. As a security key the security element 16, for example, is shaped in such a way that a closed security element 16 indicates a secure state whereas an open security element 16 presents a potentially dangerous state of an elevator installation.
    [00029] With the safety element 16 closed, the second microprocessor 15 measures, behind the safety element 16, the analog signal received via the external signaling line 17.2 of the bus node. After measurement, the second microprocessor 15 transforms the measured analog signal into a digital signal. The second microprocessor 15 finally provides the digital signal to the control unit 11.
    [00030] The safety element 16 controls, for example, the state of a cabin or pit door. With the open state of one of these doors, the security element 16 will also be open and will thus indicate the potentially dangerous state of the elevator installation. In this case, the external signaling line 17.1, 17.2 of the bus node will be interrupted. As described above, the second microprocessor 15 measures the analog signal received earlier, that is, after the security element 16. With a security element 16 in an open state, this analog signal from the second microprocessor 15 can no longer be measured. In this case, the second microprocessor 15 measures an analog signal with a fault value being 0. According to the type of analog signal, a fault current with a current value of 0 mA, a fault voltage with a voltage value of 0 mV, a fault frequency with a frequency value of 0Hz, or a fault on duration value with a on duration value of 0%. If now a fault value is measured by the second microprocessor 15, the second microprocessor 15, by virtue of the measured fault value, will spontaneously send a digital signal to the control unit 11 via the bus 12.
    [00031] Thanks to the unambiguous address of the bus node 13, the control unit 11 is able to locate the fault exactly. Eventually, the control unit 11 takes steps to remedy the fault or to transfer the elevator into a safe operational state. These operating modes include, among others, the preservation of residual availability of the elevator in a safe traveling range of the elevator cabin, the evacuation of passengers trapped inside the cabin, an emergency stop or finally the release of alarm for maintenance and maintenance personnel. services to release blocked passengers and/or to eliminate a fault that cannot be remedied by the control unit.
    [00032] The safe operation of the bus node 13 depends in the first place on the functional capacity of the first microprocessor 14 and the second microprocessor 15. In particular, it will have to be ensured that the following steps are performed without failure by the first and second microprocessor 14, 15: transformation of the standard signal into an analog signal in the first microprocessor 14, measurement of the analog signal in the second microprocessor 15, provision of the response signal by the second microprocessor 15, as well as the spontaneous behavior of the second microprocessor 15 in measuring an analog signal with a value failed.
    [00033] In a first test, the behavior of the operation of a bus node 13 in the transformation of a standard signal in normal operation will be tested. In this case, the control unit 11 issues a standard signal with a current, voltage, frequency or connection duration value in digital form to a selected bus node 13, which is done by indicating the node address of bus 13. This standard signal is renewed at certain time periods, i.e. the control unit 11 sends to the bus node 13 a standard signal with the new value of current, voltage, frequency or switching duration value. Preferably, the new value will differ from the previous value. Within a time interval of this nature, the first microprocessor 14 generates according to a standard signal a corresponding analog signal. The first microprocessor 14 subjects the internal signal line 14 of the bus node with this analog signal. The second microprocessor 15 reads this analog signal and provides the measured value as a digital response signal. In the cadence of the time interval, the control unit 11 addresses the second microprocessor 15 of the bus node 13 and, through a read function, accesses the current, voltage, frequency or connection duration data provided as a digital response signal .
    [00034] The time intervals between these pattern-query cycles can basically be freely adjusted and depend primarily on the reliability of the bus node components. Preferably, these time intervals span several seconds. With high reliability, time intervals of 100s or longer can also be set.
    [00035] Control unit 11 performs these test methods with all bus nodes 13 in sequence and tests their resonance. That is, the digital standard signals, as well as the digital response signals made available by the respective second microprocessors 15, will be checked, that is, allocated by the control unit 11. If the standard signals can be raised together with the digital response signals, the control unit 11 recognizes that the first processor 14 and the second microprocessor 15 function correctly in normal regime in transforming a standard signal.
    [00036] In a second test an open security element 16 will be simulated. The control unit 11 simulates the open safety signal 16 in that a standard signal with a fault value of 0 mA, 0 mV, 0 Hz or 0% is indicated and allocated to a given bus node 13. This standard digital signal with faulty value will be transformed by the first microprocessor 14 into an analogous signal with faulty value. In a next step, the analog signal will be subjected by the first microprocessor 14 of the signal line 18 internal to the bus node. The second microprocessor 15 measures this analogue signal and makes a spontaneous communication with the control unit 11 in the case of perfect mode of operation. This test guarantees in the positive phase that each opening of a safety element 16 leads to a spontaneous transmission of a digital response signal from the bus node 13 to the control unit 11.
    [00037] This second test will be performed periodically in repetition for each node of bus 13. The test time depends in the case, largely on the speed of data transmission by bus 12 and is normally from 50 to 100 ms. The frequency of the zero pattern test will be first according to the reliability of the second microprocessor 15 used. The more reliable the second microprocessor 15, the more rarely it will need to be tested so that safe elevator operation can be guaranteed.
    [00038] Normally, the standard test will be performed with failed value at least once a day. But this test can also be repeated in an order of minutes or hours.
    [00039] Figure 2 presents a second mode of monitoring set 10. This monitoring set 10 also comprises a control unit 11, at least one bus node 13 and a bus 12 that interconnects the control unit 11 with a node 13. This bus node 13, corresponding to the first embodiment of figure 1, has a first microprocessor 14 and a second microprocessor 15 which are interconnected without interruption via a signal line 18 internal to the bus node.
    [00040] Diverging from the first example, a contactless safety element 16.1, 16.2 is connected via an external signaling line 17 of the bus node with the second microprocessor 15. The contactless safety element 16.1, 16.2 includes here, by example, an RFID-Tag 16.2 and an RFID reader 16.1. The RFID-Tag 16.2 and the RFID-16.1 reader unit each have an induction coil. The induction coil on the side of the RFID reading unit is supplied with electrical energy and in case of a drop below a certain distance, it produces the excitation of the induction coil on the side of the RFID-Tag. In this case, the RFID-Tag 16.2 transmits a digital code value to the reading unit - RFID 16.1 through the two induction coils. The RFID reading unit 16.1 will read this digital code value and transform this code value into an analog signal with the same code value. Correspondingly, the RFID reader unit 16.1 subjects the external signaling line 17 of the bus node with the analogous signal. The second microprocessor 15 measures this analogue signal and transforms it into a digital response signal with the code value and makes it available to the control unit 11.
    [00041] The contactless safety element 16.1, 16.2 controls, for example, the state of a cabin or pit door. While this door is closed, the distance between Tag-RFID 16.2 and the reading unit - RFID 16.2 remains sufficiently reduced to enable a transfer of the digital code value. Correspondingly, the second microprocessor 15 provides a digital signal with the code value read from the RFID-Tag 16.2 of the control unit 11. With an open door, representing a potentially unsafe state of the elevator installation, it will in turn be interrupted the transmission of the code value to the reading unit - RFID 16.1. The reading unit - RFID 16.1 will therefore not read a code value, that is, a fault value. Correspondingly, the second microprocessor 15 will also measure a signal with a faulty value. In this situation, the second microprocessor 15 spontaneously transmits a digital signal to the control unit 11.
    [00042] Also in this second modality of the monitoring set 10, the reliable functional capacity of a bus node 13 will be tested with two tests.
    [00043] In a first test, the control unit 11 transmits a digital pattern signal with a first code value to the first microprocessor 14. The first microprocessor 14 transforms the pattern signal into an analog signal with the code value and subject to inner signal line 18 of the bus node. The second microprocessor 15 measures this analog signal and transforms it into a digital response signal with the measured code value. Finally, the second microprocessor 15 makes the digital response signal available to the control unit 11. The control unit 11 checks that the code value of the response signal corresponds to the code value of the standard signal. If the response signal code value can be allocated to the default signal code value, this test will be deemed to have passed. Preferably, the code value of the standard signal differs from the code value of Tag-RFID 16.2.
    [00044] The second test refers to the simulation of a faulty value and the corresponding spontaneous reaction of the second microprocessor 15. In this case, the control unit 11 sends a standard digital signal with a faulty value to the first microprocessor 14. The first microprocessor 14 transforms this standard signal into an analogue signal with the fault value and subjects the internal signal line 18 of the bus node with this analogue signal. The second microprocessor 15 measures the analog signal with the fault value and spontaneously transmits a digital feedback signal to the control unit 11. The second test will end positively when the control unit 11 checks the spontaneous reaction expected from the second microprocessor 15.
    [00045] The time intervals in which the control unit 11 sends standard signals for testing purposes to a bus node 13, can be set corresponding to the first embodiment of the control set 10.
    [00046] The two test methods of the second mode of monitoring set 10 will be performed by the control unit 11 also for each bus node 13.
    [00047] In an especially preferred alternative, the internal signaling line 18 of the bus node, in the two modes of monitoring set 10, will always be subject to a digital signal that corresponds to the differentiated values of the standard signal.
    权利要求:
    Claims (11)
    [0001]
    1. Test method of an elevator installation with a control unit (11) and at least one bus node (13) having a first microprocessor (14) and a second microprocessor (15), characterized in that the control unit (11) and the bus node (13) communicate via a bus (12) and the first microprocessor (14) and the second microprocessor (15) are interconnected without interruption through a signal line (18); with the following steps: from the control unit (11) a standard signal is transmitted to the first processor (14); the first microprocessor (14) transmits the signal over the signal line (18) to the second microprocessor (15); the second microprocessor (15) provides the signal to the control unit (11); and the control unit (11) will check whether the offered signal corresponds to a signal expected by the control unit (11).
    [0002]
    2. Test method according to claim 1, characterized in that the signal provided by the second microprocessor (15) is consulted at periodic intervals by the control unit (11).
    [0003]
    3. Test method according to claim 1, characterized in that the time interval is preferably set between 1 and 100s.
    [0004]
    4. Test method according to any of the preceding claims, characterized in that based on a negative verification of the signal provided by the control unit (11), measures will be taken to position the elevator installation in a safe operational state.
    [0005]
    5. Test method according to any of the preceding claims, characterized in that the standard signal represents a voltage value, a current value, a frequency value, a switch-on duration value or a code value .
    [0006]
    6. Test method according to any one of the preceding claims, characterized in that the signal transmitted by the first microprocessor (14) to the second microprocessor (15) is transmitted by a direct signaling line (18), especially a line flag (18) internal to the bus node.
    [0007]
    7. Test method according to any one of the preceding claims, characterized in that at least two standard signals with differentiated value are sent by the control unit (11) to the first microprocessor (14) and the control unit it checks whether the respective signal offered by the second microprocessor (15) corresponds to an expected signal from the control unit (11).
    [0008]
    8. Test method according to any one of claims 1 to 6, characterized in that a standard signal with a fault value will be sent by the control unit (11) to the first microprocessor (14) and the control unit (11) it is verified that the second microprocessor (15) spontaneously transmits a signal to the control unit (11).
    [0009]
    9. Monitoring set (10) configured to perform a test method as defined in any one of claims 1 to 8, characterized in that it has a control unit (11) and at least one bus node (13) which has a first microprocessor (14) and a second microprocessor (15), with the control unit (11) and the bus node (13) communicating through a bus (12) and the first microprocessor (14) and the second microprocessor (15) are interconnected without interruption through a signal line (18).
    [0010]
    10. Monitoring set (10) according to claim 9, characterized in that the signaling line (18) directly connects the first microprocessor (14) and the second microprocessor (15).
    [0011]
    11. Monitoring set (10) according to any one of claims 9 to 11, characterized in that the signaling line (18) is integrated inside the bus node.
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    法律状态:
    2018-12-11| B06F| Objections, documents and/or translations needed after an examination request according [chapter 6.6 patent gazette]|
    2020-01-21| B06U| Preliminary requirement: requests with searches performed by other patent offices: procedure suspended [chapter 6.21 patent gazette]|
    2021-03-09| B09A| Decision: intention to grant [chapter 9.1 patent gazette]|
    2021-04-20| B16A| Patent or certificate of addition of invention granted|Free format text: PRAZO DE VALIDADE: 20 (VINTE) ANOS CONTADOS A PARTIR DE 24/07/2012, OBSERVADAS AS CONDICOES LEGAIS. |
    优先权:
    申请号 | 申请日 | 专利标题
    EP11177268.7|2011-08-11|
    EP11177268|2011-08-11|
    EP11194235.5|2011-12-19|
    EP11194235.5A|EP2607286A1|2011-12-19|2011-12-19|Test method of an elevator system and a monitoring device for performing the test method|
    PCT/EP2012/064541|WO2013020806A1|2011-08-11|2012-07-24|Test method for an elevator system and a monitoring device for carrying out the test method|
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